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5-332 fast and ls ttl data 4-bit arithmetic logic unit the sn54 / 74ls181 is a 4-bit arithmetic logic unit (alu) which can perform all the possible 16 logic, operations on two variables and a variety of arithmetic operations. ? provides 16 arithmetic operations add, subtract, compare, double, plus twelve other arithmetic operations ? provides all 16 logic operations of two variables exclusive e or, compare, and, nand, or, nor, plus ten other logic operations ? full lookahead for high speed arithmetic operation on long words ? input clamp diodes note: the flatpak version has the same pinouts (connection diagram) as the dual in-line package. connection diagram dip (top view)

pin names loading (note a) high low a 0 a 3 , b 0 b 3 s 0 s 3 m c n f 0 f 3 a = b g p c n+4 operand (active low) inputs function e select inputs mode control input carry input function (active low) outputs comparator output carry generator (active low) output carry propagate (active low) output carry output 1.5 u.l. 2.0 u.l. 0.5 u.l. 2.5 u.l. 10 u.l. open collector 10 u.l. 10 u.l. 10 u.l. 0.75 u.l. 1.0 u.l. 0.25 u.l. 1.25 u.l. 5 (2.5) u.l. 5 (2.5) u.l. 10 u.l. 5 u.l. 5 (2.5) u.l. notes: a. 1 ttl unit load (u.l.) = 40 m a high/1.6 ma low. b. the output low drive factor is 2.5 u.l. for military (54) and 5 u.l. for commercial (74) b. temperature ranges. sn54/74ls181 4-bit arithmetic logic unit low power schottky ordering information sn54lsxxxj ceramic sn74lsxxxn plastic logic symbol

24 1 j suffix ceramic case 623-05 24 1 n suffix plastic case 649-03
5-333 fast and ls ttl data sn54/74ls181 logic diagram

functional description the sn54 / 74ls181 is a 4-bit high speed parallel arithmetic logic unit (alu). controlled by the four function select inputs (s 0 . . . s 3 ) and the mode control input (m), it can perform all the 16 possible logic operations or 16 dif ferent arithmetic operations on active high or active low operands. the function table lists these operations. when the mode control input (m) is high, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. when the mode control input is low, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. the device incorporates full internal carry lookahead and provides for either ripple carry between devices using the c n+4 output, or for carry lookahead between packages using the signals p (carry propagate) and g (carry generate), p and g are not affected by carry in. when speed requirements are not stringent, the ls181 can be used in a simple ripple carry mode by connecting the carry output (c n+4 ) signal to the carry input (c n ) of the next unit. for high speed operation the ls181 is used in conjunction with the 9342 or 93s42 carry lookahead circuit. one carry lookahead package is required for each group of the four ls181 devices. carry lookahead can be provided at various levels and of fers high speed capability over extremely long word lengths. the a = b output from the ls181 goes high when all four f outputs are high and can be used to indicate logic equivalence over four bits when the unit is in the subtract mode. the a = b output is open collector and can be wired-and with other a = b outputs to give a comparison for more then four bits. the a = b signal can also be used with the c n+4 signal to indicate a>b and a 5-334 fast and ls ttl data sn54/74ls181 function table mode select inputs active low inputs & outputs active high inputs & outputs s 3 s 2 s 1 s 0 logic (m = h) arithmetic** (m = l) (c n = l) logic (m = h) arithmetic** (m = l) (c n = h) l l l l a a minus 1 a a l l l h ab ab minus 1 a + b a + b l l h l a + b ab minus 1 a b a + b l l h h logical 1 minus 1 logical 0 minus 1 l h l l a + b a plus (a + b ) ab a plus ab l h l h b ab plus (a + b ) b (a + b) plus ab l h h l a b a minus b minus 1 a b a minus b minus 1 l h h h a + b a + b ab ab minus 1 h l l l a b a plus (a + b) a + b a plus ab h l l h a b a plus b a b a plus b h l h l b ab plus (a + b) b (a + b ) plus ab h l h h a + b a + b ab ab minus 1 h h l l logical 0 a plus a* logical 1 a plus a* h h l h ab ab plus a a + b (a + b) plus a h h h l ab ab plus a a + b (a + b ) plus a h h h h a a a a minus 1 l = low voltage level h = high voltage level * *each bit is shifted to the next more significant position **arithmetic operations expressed in 2s complement notation logic symbols active low operands active high operands

guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 v t a operating ambient temperature range 54 74 55 0 25 25 125 70 c i oh output current e high 54, 74 0.4 ma i ol output current e low 54 74 4.0 8.0 ma v oh output voltage e high (a = b only) 54, 74 5.5 v
5-335 fast and ls ttl data sn54/74ls181 dc characteristics over operating temperature range (unless otherwise specified) symbol parameter limits unit test conditions symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 54 0.7 v guaranteed input low voltage for all inputs v il input low voltage 74 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage 54 2.5 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table v oh output high voltage 74 2.7 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table v ol output low voltage except g and p 54, 74 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in = v il or v ih per truth table v ol output low voltage except g and p 74 0.35 0.5 v i ol = 8.0 ma v cc = v cc min, v in = v il or v ih per truth table v ol output g 54, 74 0.7 v i ol = 16 ma v cc = v cc min, v in = v il or v ih per truth table output p 54 74 0.6 0.5 v i ol = 8.0 ma per truth table i oh output high current 54, 74 100 m a v cc = min, i oh = max, v in = v ih or v il per truth table i ih input high current mode input any a or b input any s input c n input 20 60 80 100 m a v cc = max, v in = 2.7 v i ih mode input any a or b input any s input c n input 0.1 0.3 0.4 0.5 ma v cc = max, v in = 7.0 v i il input low current mode input any a or b input any s input c n input 0.4 1.2 1.6 2.0 ma v cc = max, v in = 0.4 v i os short circuit current (note 2) 20 100 ma v cc = max i cc power supply current see note 1a 54 32 ma v cc = max i cc power supply current see note 1a 74 34 ma v cc = max i cc see note 1b 54 35 ma v cc = max see note 1b 74 37 note 1. with outputs open, i cc is measured for the following conditions: a. s0 through s3, m, and a inputs are at 4.5 v , all other inputs are grounded. b. s0 through s3 and m are at 4.5 v , all other inputs are grounded. note 2: not more than one output should be shorted at a time, nor for more than 1 second.
5-336 fast and ls ttl data sn54/74ls181 ac characteristics (t a = 25 c, v cc = 5.0 v, pin 12 = gnd, c l = 15 pf) symbol parameter limits unit test conditions symbol parameter min typ max unit test conditions t plh t phl propagation delay, (c n to c n+4 ) 18 13 27 20 ns m = 0 v, (sum or diff mode) see fig. 4 and tables i and ii t plh t phl (c n to f outputs) 17 13 26 20 ns m = 0 v, (sum mode) see fig. 4 and table i t plh t phl (a or b inputs to g output) 19 15 29 23 ns m = s 1 = s 2 = 0 v, s 0 = s 3 = 4.5 v (sum mode) see fig. 4 and table i t plh t phl (a or b inputs to g output) 21 21 32 32 ns m = s 0 = s 3 = 0 v, s 1 = s 2 = 4.5 v (diff mode) see fig. 5 and table ii t plh t phl (a or b inputs to p output) 20 20 30 30 ns m = s 1 = s 2 = 0 v, s 0 = s 3 = 4.5 v (sum mode) see fig. 4 and table i t plh t phl (a or b inputs to p output) 20 22 30 33 ns m = s 0 = s 3 = 0 v, s 1 = s 2 = 4.5 v (diff mode) see fig. 5 and table ii t plh t phl (a x or b x inputs to f x output) 21 13 32 20 ns m = s 1 = s 2 = 0 v, s 0 = s 3 = 4.5 v (sum mode) see fig. 4 and table i t plh t phl (a x or b x inputs to f x output) 21 21 32 32 ns m = s 0 = s 3 = 0 v, s 1 = s 2 = 4.5 v (diff mode) see fig. 5 and table ii t plh t phl (a x or b x inputs to f xh outputs) 38 26 ns m = s 1 = s 2 = 0 v, s 0 = s 3 = 4.5 v (sum mode) see fig. 4 and table i t plh t phl (a x or b x inputs to f xh outputs) 38 38 ns m = s 0 = s 3 = 0 v, s 1 = s 2 = 4.5 v (diff mode) see fig. 5 and table ii t plh t phl (a or b inputs to f outputs) 22 26 33 38 ns m = 4.5 v (logic mode) see fig. 4 and table iii t plh t phl (a or b inputs to c n+4 output) 25 25 38 38 ns m = 0 v, s 0 = s 3 = 4.5 v, s 1 = s 2 = 0 v (sum mode) see fig. 6 and table i t plh t phl (a or b inputs to c n+4 output) 27 27 41 41 ns m = 0 v, s 0 = s 3 = 0 v, s 1 = s 2 = 4.5 v (diff mode) t plh t phl (a or b inputs to a = b output) 33 41 50 62 ns m = s 0 = s 3 = 0 v, s 1 = s 2 = 4.5 v r l = 2.0 k w (diff mode) see fig. 5 and table ii ac waveforms figure 5 figure 6 figure 4

5-337 fast and ls ttl data sn54/74ls181 sum mode test table i function inputs: s 0 = s 3 = 4.5 v, s 1 = s 2 = m = 0 v parameter input under test other input same bit other data inputs output under test parameter input under test apply 4.5 v apply gnd apply 4.5 v apply gnd output under test t plh t phl a l b l none remaining a and b c n f l t plh t phl b l a l none remaining a and b c n f l t plh t phl a l b l none c n remaining a and b f l+1 t plh t phl b l a l none c n remaining a and b f l+1 t plh t phl a b none none remaining a and b , c n p t plh t phl b a none none remaining a and b , c n p t plh t phl a none b remaining b remaining a , c n g t plh t phl b none a remaining b remaining a , c n g t plh t phl a none b remaining b remaining a , c n c n+4 t plh t phl b none a remaining b remaining a , c n c n+4 t plh t phl c n none none all a all b any f or c n+4
5-338 fast and ls ttl data sn54/74ls181 diff mode test table ii function inputs: s 1 = s 2 = 4.5 v, s 0 = s 3 = m = 0 v parameter input under test other input same bit other data inputs output under test parameter input under test apply 4.5 v apply gnd apply 4.5 v apply gnd output under test t plh t phl a none b remaining a remaining b , c n f l t plh t phl b a none remaining a remaining b , c n f l t plh t phl a l none b l remaining b , c n remaining a f l+1 t plh t phl b l a l none remaining b , c n remaining a f l+1 t plh t phl a none b none remaining a and b , c n p t plh t phl b a none none remaining a and b , c n p t plh t phl a b none none remaining a and b l , c n g t plh t phl b none a none remaining a and b , c n g t plh t phl a none b remaining a remaining b , c n a = b t plh t phl b a none remaining a remaining b , c n a = b t plh t phl a b none none remaining a and b , c n c n+4 t plh t phl b none a none remaining a and b , c n c n+4 t plh t phl c n none none all a and b none c n+4 logic mode test table iii parameter input under test other input same bit other data inputs output under test function inputs parameter input under test apply 4.5 v apply gnd apply 4.5 v apply gnd output under test function inputs t plh t phl a none b none remaining a and b , c n any f s 1 = s 2 = m = 4.5 v s 0 = s 3 = 0 v t plh t phl b none a none remaining a and b , c n any f s 1 = s 2 = m = 4.5 v s 0 = s 3 = 0 v
5-339 fast and ls ttl data case 623-05 j suffix 24-pin ceramic dual in-line (wide body)

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5-340 fast and ls ttl data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . literature distribution centers: usa: motorola literature distribution; p .o. box 20912; phoenix, arizona 85036. europe: motorola ltd.; european literature centre; 88 t anners drive, blakelands, milton keynes, mk14 5bp , england. jap an: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, t okyo 141, japan. asia p acific: motorola semiconductors h.k. ltd.; silicon harbour center , no. 2 dai king street, t ai po industrial estate, t ai po, n.t., hong kong. ?

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